1. Field of the Invention
The present invention relates to a clock distribution circuit and, in particular, to a clock distribution circuit having a clock gating circuit.
2. Description of the Related Art
As semiconductor integrated circuits have increased in scale and speed in recent years, power consumption in the semiconductor integrated circuits has also become a matter of utmost concern. As a technique for reducing power consumption in semiconductor integrated circuits, a method of controlling a clock signal by a clock gating circuit has been known.
The clock gating circuit stops supply of the clock signal to a flip-flop (hereinafter abbreviated as FF) circuit when a memory element, for example the FF, does not need to be supplied with a clock signal. That is, when supplying a clock signal that does not update the content of the FF, the clock gating circuit fixes the clock signal at “0” or “1”. This reduces the number of level changes of the clock signal and therefore can reduce power consumption in the circuit. Clock distribution circuits that use such a clock gating circuit to reduce power consumption in logic circuits have been proposed (for example see Japanese Patent Application Laid-Open Publication No. 2006-3249).
A conventional clock distribution circuit includes a phase-locked loop (PLL) which generates clock signals with different frequencies, a clock gating circuit, a clock tree, multiple FFs connected to an end of the clock tree, and a combinational circuit which generates a clock gating signal on the basis of an output or outputs from one or more FFs.
The clock tree consists of buffers with an identical driving performance connected in the form of a tree in order to supply a clock signal from the PLL to many FFs in the same phase. Accordingly, clock signals appearing at the ends of the clock tree are in phase with each other but are delayed from the clock signal at the root of the clock tree by several nanoseconds. In general, as the number of FFs connected increases, the number of buffer stages of the clock tree increases and so does the amount of the delay of the clock signal that propagated through the clock tree.
Part of FFs connected at the ends of the clock tree generate, on the basis of the delayed clock signal, control signals from which clock gating signals are generated. The combinational circuit generates a clock gating signal on the basis of the generated control signals. That is, in addition to an amount of delay produced by the clock tree, an amount of delay produced by logic gates included in the combinational circuit for generating the clock gating signal are added to the clock gating signal.
The clock gating circuit has the function of passing or blocking a clock signal depending on the value of the clock gating signal. For example, when the value of the clock gating signal is “1”, the clock gating circuit passes the clock signal; when the value of the clock gating signal is “0”, the clock gating circuit blocks the clock signal.
However, since the clock gating circuit uses a clock gating signal to which an amount of delay produced by the clock tree and logic gates is added to control an undelayed clock signal, that is, a clock signal from the PLL, a path including the clock gating signal is subject to a severe timing constraint. In particular, the amount of delay time allowable in the combinational circuit provided between the FF at an end of the clock tree and the clock gating circuit is smaller.
Furthermore, as the number of FFs has increased and clock frequencies have also increased recently, amounts of delay produced by a clock tree and logic gates appear relatively large. Therefore, there is a problem that a timing violation occurs in a path including a clock gating signal when the amount of delay of signal propagation increases due to a power supply voltage drop or a chip temperature rise, for example, under severe operating conditions.